Home Articles FAQs XREF Games Software Instant Books BBS About FOLDOC RFCs Feedback Sitemap
irt.Org

Staggered Pin Grid Array

You are here: irt.org | FOLDOC | Staggered Pin Grid Array

<hardware> (SPGA) A style of integrated circuit socket or pin-out with a staggered grid of pins around the edge of the socket, positioned as several squares, one inside the other.

SPGA is commonly used on motherboards for processors, e.g. Socket 5, Socket 7 and Socket 8.

See also PGA.

[Better description?]

(1999-08-04)

Nearby terms: stack puke « stack traceback « STAGE2 « Staggered Pin Grid Array » staircase » staircasing » stale pointer bug

FOLDOC, Topics, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, ?, ALL

©2018 Martin Webb